6byte Add. + 58bytes capture
worst case 58*8 / 10Mbps = 46,4 mueSek. to respond

the parallel interface use busffer descriptor look up, into 32bit FIFO width memory bus
is bound by the 4-longword SCC2 receive FIFO leaving 42 Bytes or 33,6 mueSek of respons time

the MU9C1480 LAN CAM holds 1K 64bit can cascaded to achieve deeper CAM size
device uses a 16bit Data BUS in a 44PIN pllc
letch the destination address 32bit data bus comparing the sequenz to writing it in register by 16bit words.

the interface logic allow also host access to the LANCAM for Add Tabel maintenance.

also a DSP can use as an address filter, with a fast instruction cycle Time (30 to 50 ns)
Communication with the CPU is done (3DC++) via an independent parallel Host Port on the DSP
_{the hostport is used to boodstrap the DSP}

the Motorola DSP56002 by 24Bit using 66Mhz for 30ns execution time!
with 56bit accomulation which allows a full 48bit Ethernet address to be DONE in a single intruction _{(3x by MT6261)}
internal dataRAM of 512 WORDs each for address filter code an up to 256 Addresses inkl. destination ADD
^{Optional the MCM56824 expand the static RAM to 8K words}

• Offset corresponds to the bits used to determine the byte to be accessed from the cache line. Because the cache lines are 4 bytes long, there are 2 offset bits.
• Index corresponds to bits used to determine the set of the Cache. There are 32 sets in the cache, and because 2^5 = 32, there are 5 index bits.
• Tag corresponds to the remaining bits. This means there are 14 – (5+2) = 7 bits, which are stored in tag field to match the address on cache request.

1 bit frame sync signal to start receiving
the first 3Bit used to delay the DATA! and than starts the INVERSION auf 24Bit WORDS in time slots
after 2 WORDS received its RESET the SSI and starting all again ...next FRAME
Trilling back and forth , 2WORD Destination Reset then 2 WORD Source

The letching VALUE $FF to compare the 48Bits at a TIME can be later FILTERED by the MCU
The Address Table consisting X and Y memory Location to take advantage of the parallel architecture
By comparing the destination ADD (56bit), the end of search is detected.
the Table Pointer goes back to the next parallel LOAD or EXIT
the searching LOOp needs 3 instruction Cycles to execute it to onCHIP RAM table, therefore it needed an extra CYCLE to TRANFER the 48Bit ADD on the SINGLE BUS!

# ADDRESS ENTRIES

• MU91480
  ≶1023
• NxMU9C1408
  ≶ N x 1022
  Mutiple CAMs
• DSP 40MHz
  <255
• DSP 66MHz
  >500
  External Memomry

AT 3 cycles (90ns) per address, can go through roughly 500 address entries withinthe shartest Ethernet frame.
A small bridge with up to 255 address table entries would only the lower cost by 40Mhz using only On.Chip.Memory
by 60Mhz external Memory, device can HANDLE 500entries! Thats usable for Multiple DSPs in Parallel!

FAZIT

When multiple requests arrive at the CP to be serviced, they are handled in the following priority order

1. Highest Reset in CP command register or System Reset
2. SDMA bus error
3. Commands issued in the CP command register
4. SCC1 reception
5. SCC1 transmission
6. SCC2 reception
7. SCC2 transmission
8. SCC3 reception
9. SCC3 transmission
10. SCC4 reception
11. SCC4 transmission
12. SMC1 reception
13. SMC1 transmission
14. SMC2 reception
15. SMC2 transmission
16. SPI reception
17. SPI transmission
18. PIP
19. Lowest RISC Timers

The MC68360 Quad Integrated Communications Controller (QUICC) has many seven controllers

Under extreme conditions, too many requests can arrive at the CP in a given period for it to handle. In this case, the lower priority requests are ignored. When this is a serial channel, its FIFOs will underrun or overrun cause problems elsewhere in the system.
Controlling the serial periphal interface (SPI) by two (SMCs) serial management controllers under FOUR (SCCs) serial communication controlers.

When all sixteen RISC timers are operating, they use approximately 4% of the CP performance. If other CP activity exceeds a 96% utilisation of the CP, the RISC counters will not increment regularly. performance testing is complete and the RISC timers are not running, there is approximately 4% spare capacity in the CP to handle other requests

CPM / CPU Interaction

On transmit, the SDMA will either read 16 or 32-bits at the start of a frame depending on the starting address. (If a 16-bit read is sufficient, the SDMA will only read 16-bits). It then throws away one of the bytes if it does not need all of them. Then for the rest of the transfers, the SDMA will always read 32-bits at a time. Note: The SDMA only reads 16-bits at a time in UART mode, and never reads 32-bits.

• SCC Parameter RAM
• What the commands really do
• How a Frame Gets Transmitted
• How a Frame Gets Received
• Performance ISSUES
• SDMA Behavior

(SCC1 TX immediately followed by SCC2 TX). There will always be a few clocks inbetween

As soon as there is one 32-bit entry of the receive FIFO that is available, a request is generated to the CPM. _{This provides the maximum bus latency. Minimum bus latency allowed is therefore the time it takes to fill N-4 bytes, where N is the number of bytes in the FIFO (either 32 for SCC1, or 16 for the other SCCs)}

Long frames are better because there is more time In Frame to recover from the high CPM loading of opening/closing BDs.

CPM will use multiple buffers to receive a frame if needed

CPM pipelines its reads so up to 9 clocks latency has no performance impact at all!

After the entire frame is transmitted, the CPM will check the next BD’s ready bit immediately. If 0, it will go back into 128 tx clock poll mode.

CPM does an SDMA cycle(s) to write the first 32-bits of receive data.

CPM Detects Ready bit has been set. »After this SCC goes idle, the CPM polls the ready bit every 128 TX Clocks for Ethernet, (64 TX Clocks for HDLC/Transparent and every character time for UART).

CPM does an SDMA cycle(s) to get the first 32-bits of transmit data

Host Commands from CPU | Buffer Descriptors | Event Registers | Configuration Registers

(1x) = A10 Stack Pointer

(2x) = OS Processes

(3X) = Threads

• handels 4 and 6 bit C/I code reception and transmission automatically
• all receiver DAta is timestampd
• handels 2,4,8, or 16 ISDN lines with full C/I and monitor channel functions
• handels up to 32 ISDN lines with only C/I channels
• handels GCI monitor messages from 1 to 64 Kilobytes in length
• operates independently of MCU activity
• Consumes 1280bytes of MCU intern memory

A typical 16-Subscriber ISDN line card using MGSCI in an ISDN switch. Each subscriber line is terminated on the line card by a U or S/t line transeiver. The Multiplexer logic converts between the 16 individual basic rate GCI circuits and time devision multiplex links carrying the D, B ans control Channels. The B Channels are routed to the main system via the system interface while the D.Channels are handeld on the board. The C/I and monitor channels are used on the board to carry control and status information between the MC68360 and the Transceiver.

WIth 25MHZ of processing POWER of a RISC communication engin by an MGCI SCC operation at a serial bit rate of 2Mbps carries 32 x 64Kbit channels.

ASYNCHRONOUS HDLC FOR PPP

ASYNC HDLC is a frame based protocol which uses HDLC framing techniques in conjunction with UART-type characters. Used as the Physical layer for the Point to Point Protocol (PPP).

It is more efficient and less cumpute-intenive for the CPU to allow the Communication Processor Modul (CPM) to perform the framing and transparency functions of the protocol.

At 25MHz, an aggregate Asynchronous HDLC bandwidth of 3Mbps divided among 4 SCCs consumes 100% of the processing POWER!

Seperate interrupts for receiving frames and transmitted buffers

Automatic 16Bit CRC generating and checking (CRC-CCITT)

Automatic transmission of the ABORT sequens (0x7D, 0x7E) after the STOP TRANSMIT command is issued.

Consumes of the 768Bytes of the MCUs intern Memory 0> 768/2=384*8=3072 | *125 = 384000/pixel